User Guide
Page 13
...integer pipelines, three address calculation pipelines, and a superscalar, fully pipelined, out-of the AMD Athlon XP processor model 6 are QuantiSpeed™ architecture, a high-performance full-speed cache, a 266-MHz, 2.1-Gigabyte per second system bus, and 3DNow!™ Professional technology...class Computer-Aided Design (CAD), commercial desktop publishing, and speech recognition. The AMD Athlon XP processor model 6 also offers the scalability and reliability that include high-speed Internet capability, digital content creation, digital photo editing, digital video, image compression...
...integer pipelines, three address calculation pipelines, and a superscalar, fully pipelined, out-of the AMD Athlon XP processor model 6 are QuantiSpeed™ architecture, a high-performance full-speed cache, a 266-MHz, 2.1-Gigabyte per second system bus, and 3DNow!™ Professional technology...class Computer-Aided Design (CAD), commercial desktop publishing, and speech recognition. The AMD Athlon XP processor model 6 also offers the scalability and reliability that include high-speed Internet capability, digital content creation, digital photo editing, digital video, image compression...
User Guide
Page 17
...contained within the Socket A socket. Chapter 2 Interface Signals 5 24309E-March 2002 Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 2 Interface Signals 2.1 Overview The AMD Athlon™ system bus architecture is designed to deliver excellent data movement bandwidth for nextgeneration x86 ...is asserted or deasserted by the source. The system bus architecture consists of three high-speed channels (a unidirectional processor request channel, a unidirectional probe channel, and a 64-bit bidirectional data channel), source-synchronous clocking, and a ...
...contained within the Socket A socket. Chapter 2 Interface Signals 5 24309E-March 2002 Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 2 Interface Signals 2.1 Overview The AMD Athlon™ system bus architecture is designed to deliver excellent data movement bandwidth for nextgeneration x86 ...is asserted or deasserted by the source. The system bus architecture consists of three high-speed channels (a unidirectional processor request channel, a unidirectional probe channel, and a 64-bit bidirectional data channel), source-synchronous clocking, and a ...
User Guide
Page 30
... STPCLK# deassertion) occurs. B Issue a Connect special cycle.* C Return internal clocks to full speed and assert PROCRDY. Note: * The Connect special cycle is only issued after a subsequent processor wake-up event). Processor Connect State Diagram 18 Power Management Chapter 4 Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002 1 Disconnect Pending 3/A Connect 2/B Disconnect 6/B Connect Pending...
... STPCLK# deassertion) occurs. B Issue a Connect special cycle.* C Return internal clocks to full speed and assert PROCRDY. Note: * The Connect special cycle is only issued after a subsequent processor wake-up event). Processor Connect State Diagram 18 Power Management Chapter 4 Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002 1 Disconnect Pending 3/A Connect 2/B Disconnect 6/B Connect Pending...
User Guide
Page 92
Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002 Table 23. Acronyms Abbreviation Meaning ACPI Advanced Configuration and Power Interface AGP Accelerated Graphics Port ...Electronics EISA Extended Industry Standard Architecture EPROM Enhanced Programmable Read Only Memory FIFO First In, First Out GART Graphics Address Remapping Table HSTL High-Speed Transistor Logic IDE Integrated Device Electronics IPC Instructions Per Cycle ISA Industry Standard Architecture JEDEC Joint Electron Device Engineering Council 80 Appendix A Table...
Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002 Table 23. Acronyms Abbreviation Meaning ACPI Advanced Configuration and Power Interface AGP Accelerated Graphics Port ...Electronics EISA Extended Industry Standard Architecture EPROM Enhanced Programmable Read Only Memory FIFO First In, First Out GART Graphics Address Remapping Table HSTL High-Speed Transistor Logic IDE Integrated Device Electronics IPC Instructions Per Cycle ISA Industry Standard Architecture JEDEC Joint Electron Device Engineering Council 80 Appendix A Table...