User Guide
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Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002 8 Signal and Power-Up Requirements 43 8.1 Power-Up Requirements 43 Signal Sequence and Timing Description 43 Clock Multiplier Selection (FID[3:0 46 8.2 Processor Warm Reset Requirements 46 Northbridge Reset Pins 46 9 Mechanical Data 47 9.1 Introduction 47 9.2 Die Loading 47 9.3 OPGA Package Description 48 10 Pin...
Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002 8 Signal and Power-Up Requirements 43 8.1 Power-Up Requirements 43 Signal Sequence and Timing Description 43 Clock Multiplier Selection (FID[3:0 46 8.2 Processor Warm Reset Requirements 46 Northbridge Reset Pins 46 9 Mechanical Data 47 9.1 Introduction 47 9.2 Die Loading 47 9.3 OPGA Package Description 48 10 Pin...
User Guide
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... APIC Pin AC and DC Characteristics 41 Mechanical Loading 47 Dimensions for the AMD Athlon XP Processor Model 6 OPGA Package 48 Pin Name Abbreviations 54 Cross-Reference by Pin Location 60 FID[3:0] Clock Multiplier Encodings 70 VID[4:0] Code to Voltage Definition 74 Abbreviations 79 Acronyms 80 List of Tables Table 1. Table 8. Table 23. Table 12...
... APIC Pin AC and DC Characteristics 41 Mechanical Loading 47 Dimensions for the AMD Athlon XP Processor Model 6 OPGA Package 48 Pin Name Abbreviations 54 Cross-Reference by Pin Location 60 FID[3:0] Clock Multiplier Encodings 70 VID[4:0] Code to Voltage Definition 74 Abbreviations 79 Acronyms 80 List of Tables Table 1. Table 8. Table 23. Table 12...
User Guide
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... within specification. VCCA must be within specification. The reference system 44 Signal and Power-Up Requirements Chapter 8 The AMD Athlon XP processor model 6 does not set the correct clock multiplier if PWROK is asserted. Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002 Power-Up Timing Requirements. This delay ensures that VCC_CORE and all other...
... within specification. VCCA must be within specification. The reference system 44 Signal and Power-Up Requirements Chapter 8 The AMD Athlon XP processor model 6 does not set the correct clock multiplier if PWROK is asserted. Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002 Power-Up Timing Requirements. This delay ensures that VCC_CORE and all other...
User Guide
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..., CONNECT, and CLKFWDRST signals, that determines the processor frequency indicated by the FID[3:0] code. Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002 Clock Multiplier Selection (FID[3:0]) The chipset samples the FID[3:0] signals in a chipset-specific manner from the processor and uses this information to AMD Athlon™ and AMD Duron™ System Bus Specification, order...
..., CONNECT, and CLKFWDRST signals, that determines the processor frequency indicated by the FID[3:0] code. Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002 Clock Multiplier Selection (FID[3:0]) The chipset samples the FID[3:0] signals in a chipset-specific manner from the processor and uses this information to AMD Athlon™ and AMD Duron™ System Bus Specification, order...
User Guide
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...21. This CLK_Ctl setting is used with all ratios of 12.5x or greater to be sampled until they become valid. Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002 FID[3:0] Pins FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1...determine the SIP (Serialization Initialization Packet) that are open drain processor outputs that is sent to -SYSCLK ratio. The FID[3:0] signals are the 4-bit processor clock-to the processor. FID[3:0] Clock Multiplier Encodings FID[3:0]2 Processor Clock to 6003_D22Fh during the POST routine. The FID[3:0]signals...
...21. This CLK_Ctl setting is used with all ratios of 12.5x or greater to be sampled until they become valid. Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002 FID[3:0] Pins FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1...determine the SIP (Serialization Initialization Packet) that are open drain processor outputs that is sent to -SYSCLK ratio. The FID[3:0] signals are the 4-bit processor clock-to the processor. FID[3:0] Clock Multiplier Encodings FID[3:0]2 Processor Clock to 6003_D22Fh during the POST routine. The FID[3:0]signals...