Design Guide
Page 42
... and Pentium II processors. MTRR0 (lower 32 bits of the UWCCR register) defines the size and memory type of range 0 and MTRR1 (upper 32 bits) defines the size and memory type of the UWCCR is applicable for linear video frame buffers. The processor conditionally combines.... The MSR address of range 1 (see Figure 7 on page 31). Merging multiple write cycles into a merge buffer. Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 UC/WC Cacheability Control Register (UWCCR) Models 8/[F:8], 9, and D provide two variable-range Memory Type Range ...
... and Pentium II processors. MTRR0 (lower 32 bits of the UWCCR register) defines the size and memory type of range 0 and MTRR1 (upper 32 bits) defines the size and memory type of the UWCCR is applicable for linear video frame buffers. The processor conditionally combines.... The MSR address of range 1 (see Figure 7 on page 31). Merging multiple write cycles into a merge buffer. Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 UC/WC Cacheability Control Register (UWCCR) Models 8/[F:8], 9, and D provide two variable-range Memory Type Range ...