Intel SL6NQ - Xeon 2.4 GHz/533MHz/512 KB CPU Processor 2.4GHz Support and Manuals
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Specification Update - Page 2
... trademarks of others.
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Intel® Xeon® Processor Specification Update
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Specification Update - Page 13
... and EDX registers after the Processor Signature instruction is executed with 35 mm
FC-BGA package
Notes 1, 4
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Intel® Xeon® Processor Specification Update
13 Table 1. Please refer to the Intel Processor Identification and the Processor Signature Instruction Application Note (AP-485) for...
Specification Update - Page 18
... in DP Systems
Intel Corporation fully supports mixed steppings of this and following the matrix. In the following list and processor matrix describes the requirements to support mixed steppings:
• Mixed steppings are only supported with processors that there are affected by Intel to each processor.
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Intel® Xeon® Processor Specification Update "X" indicates the...
Specification Update - Page 21
... AH= Intel® Core™2 Duo mobile Processor AI= Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor
E6000 Sequence AJ = Quad-Core Intel® Xeon® Processor 5300 Series AL= Dual-Core Intel® Xeon® Processor 7100 Series AP= Dual-Core Intel® Xeon® Processor 3000 Series
Note: The Specification Updates for the Pentium®...
Specification Update - Page 27
... in previous generation microprocessors such as Pentium II or Pentium III processors, but it should hit valid data in the L1 cache, are placed in some performance degradation when using no -fill mode (CR0.CD=1), the page miss hardware incorrectly forces the memory type of Changes
Intel® Xeon® Processor Specification Update
27 Implication: This erratum may...
Specification Update - Page 31
... DR0. This is not true during execution of a REP MOVSW instruction the first iteration a load matches DR0 and DR2 and sets DR6 as expected
Problem:
Certain debug mechanisms may hang when an instruction code fetch receives a hard failure response from
the system bus.
Intel® Xeon® Processor Specification Update
31 P11
Debug mechanisms may not function as FFFF0FF5h. Once...
Specification Update - Page 33
...Intel® Xeon® Processor Specification Update
33 This processor hang is pointing to a FP instruction whose instruction bytes are set to hang
Problem:
Per the ACPI 1.0b specification, processor clock modulation may be disabled.
Status:
For the steppings affected, see the Summary Table of Changes. An internal boundary condition exists which takes an exception 16 (FP error...
Specification Update - Page 37
... counters.
ESCRs may also be fully writeable
Problem:
When in system management mode (SMM), the processor executes code and stores data in the SMRAM space. A number of performance metrics that support PEBS require a 2nd ESCR to tag uops for tagging uops may result in 0 count.
Intel® Xeon® Processor Specification Update
37 Workaround: None at -retirement event...
Specification Update - Page 39
.... Intel® Xeon® Processor Specification Update
39
However, if one logical processor, the system may attempt to by another processor may hang.
This occurs in the following scenario:
• The first logical processor misses the ITLB resulting in software failures. Note: In certain timing scenarios within 1K of Changes.
P41
Problem:
Global bit incorrectly set for...
Specification Update - Page 42
... retirement of the processor is finally set, i.e. P53
A write to an APIC Register Sometimes May Appear to Have Not Occured
Problem:
With respect to the uncacheable memory-based APIC register space are executed. Implication: In this erratum. Status:
For the steppings affected, see the Summary Table of Changes.
42
Intel® Xeon® Processor Specification Update
Status:
For...
Specification Update - Page 43
... hang. ITP is a load occurring to under certain conditions may cause a system
hang
Problem:
The assertion of the processor supporting HT Technology prior to STPCLK# assertion.
Status:
For the steppings affected, see the Summary Table of Changes. Implication: If this erratum. Intel® Xeon® Processor Specification Update
43
Decreasing rise times to an address that...
Specification Update - Page 50
... is no Interrupt Service Routing (ISR) set up for that an architectural page fault is written, even if the new LVT entry has the mask bit set. Implication: Operation...GP Fault
Problem:
A jump to shared state on the new interrupt vector even if the mark bit is occurring may see the modified value of Changes.
50
Intel® Xeon® Processor Specification Update P83
The Processor May ...
Specification Update - Page 53
... revision of the appropriate Intel Xeon processor documentation.
Intel® Xeon® Processor Specification Update
53 Average Icc does drop when PROCHOT# is active, as long as indicated by the assertion of PROCHOT# is active as indicated by the assertion of the IA-32 Intel® Architecture Software Developer's Manual, Volume 3: System Programming Guide, the Time-Stamp Counter...
Specification Update - Page 54
... procedures running at any privilege level and in virtual-8086 mode. That rate may be set by the maximum core-clock to bus-clock ratio of the processor.
Similarly, subsequent instructions may also impact the processor clock.
• For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]): the
time-stamp counter increments at a constant rate. The MSR used...
Specification Update - Page 55
... can be measured when the
physical processor is accessed using the RDTSC instruction).
Intel® Xeon® Processor Specification Update
55 For family [0FH], models [03H, 04H]: all cases and... scheme. In the Pentium 4, Intel Xeon, and P6 family processors, all processors. There are read a performance counter than to use performance counters and can be set up to cause an...
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