Intel SL3VS - Celeron 633 MHz Processor Support and Manuals
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Specification Update - Page 12
.... INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
IDENTIFICATION INFORMATION
Complete identification information of the Celeron processor can be identified by the following values:
Family1
Model2
Brand ID3
0110
0101
00h = Not Supported
0110 0110 0110
0110
1000 10114
00h = Not Supported 01h = "Intel® Celeron® Processor" 03h = "Intel® Celeron® Processor...
Specification Update - Page 14
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
S-Spec SL3A2 SL37X SL3BA SL3BS SL3EH SL3FL SL3FY SL3LQ SL3FZ SL3PZ SL46S SL3W6 SL46T SL3W7 SL4PC SL4NW SL5L5 SL46U SL3W8 SL4PB SL4NX SL3VS SL3W9 SL4PA SL4NY SL48E SL4AB SL4P9 SL4NZ
Intel® Celeron® Processor Identification Information
Core Stepping
B0
L2 Cache Size
(Kbytes)
128
CPUID 0665h
Speed (MHz) Core/Bus
400/66
Package ...
Specification Update - Page 19
...There are used in Intel's microprocessor Specification Updates: A = Dual-Core Intel® Xeon® processor 7000 sequence C = Intel® Celeron® processor D = Dual-Core Intel® Xeon® Processor 2.80 GHz E = Intel® Pentium® III processor F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor I = Dual-Core Intel® Xeon®...
Specification Update - Page 20
... be set
C5
X
X
X
X
X
X
X
X
X NoFix BTM for SMI will contain
incorrect FROM EIP
C6
X
X
X
X
X
X
X
X
X NoFix I/O restart in 478 Pin Package AD = Intel® Celeron® D processor on 65 nm process AE = Intel® Core™ Duo Processor and Intel® Core™ Solo processor on 65 nm process AF = Dual-Core Intel® Xeon® processor LV AG = Dual-Core Intel®...
Specification Update - Page 34
... an instruction fetch will fail, if this problem by case 4. Case 3: If they become disabled. If one other breakpoint is enabled, corresponding to all tasks, respectively. However, if the address in a disabled register matches the address of this information under these registers are disabled (i.e., Ln and Gn are disabled. INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE...
Specification Update - Page 46
...the core ...processor are valid and stable. INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
C25. no transactions intervening, may have a side-effect style of a read-write or read-read -modify-write (RMW) arithmetic instruction...drivers for the occurrence of the initial load may not be initialized.
Read Portion of RMW Instruction May Execute Twice
Problem: When the Celeron processor...
Specification Update - Page 47
...3: System Programming Guide, documents that the exception did occur in V86 mode, the exception may be generated, as documented in V86 mode before continuing. However, for the MCi_STATUS MSR, bits 15:0 contain the MCA (machine-check architecture) error code fields and bits 31:16 contain the model-specific error code field.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
Status: For...
Specification Update - Page 48
...the value in their default setting, which must all eight ...Intel Architecture Software Developer's Manual, Volume 3: System Programming Guide, for details), data for 4-Kbyte pages. Upper Four PAT Entries Not Usable With Mode B or Mode C Paging
Problem: The Page Attribute Table (PAT) contains eight entries, which includes UC- INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE...
Specification Update - Page 57
...CELERON® PROCESSOR SPECIFICATION UPDATE
C49. Intel processors detect the attempted execution of the available op-code space; The necessary conditions for the deadlock involve:
1. FLUSH# Assertion Following STPCLK# May Prevent CPU Clocks From Stopping
Problem: If FLUSH# is asserted after STPCLK# is asserted, the cache flush operation will normally flag such a sequence as an error...
Specification Update - Page 74
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
C83. this erratum was discovered in the shadow of the JMP FAR instruction could lead to erroneous software behavior. Processor Does not .... One of this erratum, CLTS, is a privileged instruction that is corrected by an operating system or driver code.The remaining three instructions, POPSS, LSS, and MOV to this condition; Due...
Specification Update - Page 80
...when a LVT entry is no Interrupt Service Routine (ISR) set the reserved bits to memory regions ...Problem:
Invalid entries in Page-Directory-Pointer-Table Register (PDPTR) May Cause General Protection (#GP) Exception if the Reserved Bits are invalid.
This ISR routine must have the reserved bits set .
C98.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE...
Specification Update - Page 81
..., to not be serviced until the interrupt enabled... set, i.e.
Status:
For the steppings affected, see the Summary Tables of instructions,...instructions are met, address bit 20 may allow interrupts to be masked (forced to zero) to emulates real-address mode address wraparound at 1 megabyte. Intel has not observed this erratum. INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
Problem...
Specification Update - Page 89
... FOP is only valid if the last non-transparent FP instruction executed before a FSAVE/FSTENV/FXSAVE).
FCOS, FPTAN, FSIN, and FSINCOS Trigonometric Domain
NOT correct. INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
It should state: C2
Set to 1 if outside the range -263 to +263; If FOP code compatibility mode is disabled (default), FOP is defined as it...
Specification Update - Page 95
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE
15. Entry PMULL currently states: PMULL - Correct MOVAPS and MOVAPD Operand Section
The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference Section 3.2 "INSTRUCTION REFERENCE" MOVAPS and MOVAPD operation section currently states:
Operation DEST Å SRC; RSM Instruction Set Summary
The Intel Architecture ...
Specification Update - Page 99
... Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference Section 3.2 Instruction ...Intel Architecture Software Developer's Manual, Vol 1: Basic Architecture, page 12-6, section 12.5.2, last paragraph currently states:
If the I /O instructions generate exceptions when the CPL is greater than or equal to DFFFH. INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE...
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