Data Sheet
Page 7
... section that E-step of the X5482 falls into the 120W X5400 family. Added product information for the Quad-Core Intel® Xeon® Processor L5408. Corrected L1 cache size Introduced X5492 Updated X5482 power levels on E-step Maintains change bars from version 004. Revision History ...Revision 001 002 003 004 005 Description Initial release Added product information for the Quad-Core Intel® Xeon® Processor L5400 Series. ...
... section that E-step of the X5482 falls into the 120W X5400 family. Added product information for the Quad-Core Intel® Xeon® Processor L5408. Corrected L1 cache size Introduced X5492 Updated X5482 power levels on E-step Maintains change bars from version 004. Revision History ...Revision 001 002 003 004 005 Description Initial release Added product information for the Quad-Core Intel® Xeon® Processor L5400 Series. ...
Data Sheet
Page 9
... viruses that can improve virtualization 9 The Quad-Core Intel® Xeon® Processor 5400 Series support Intel® Virtualization Technology for data movement. Further details on -die, primary 32-kB instruction cache and 32-kB write-back data cache in conjunction with IA-32 software. Quad-Core Intel® Xeon® Processor 5400 Series features include Intel® Wide Dynamic Execution, enhanced...
... viruses that can improve virtualization 9 The Quad-Core Intel® Xeon® Processor 5400 Series support Intel® Virtualization Technology for data movement. Further details on -die, primary 32-kB instruction cache and 32-kB write-back data cache in conjunction with IA-32 software. Quad-Core Intel® Xeon® Processor 5400 Series features include Intel® Wide Dynamic Execution, enhanced...
Data Sheet
Page 10
... transfers data four times per core L2 Advanced Cache 2x6 MB shared Front Side Bus Frequency 1600 MHz 1333 MHz 1066 MHz Package FC-LGA 771 Lands The Quad-Core Intel® Xeon® Processor 5400 Series-based platforms implement independent core voltage (VCC) power planes for...in AGP 4X). For example, when RESET# is high, a nonmaskable interrupt has occurred. The Quad-Core Intel® Xeon® Processor 5400 Series is inverted. It utilizes a surface mount LGA771 socket that the signal is intended for improved power delivery. The FSB utilizes a split-transaction, ...
... transfers data four times per core L2 Advanced Cache 2x6 MB shared Front Side Bus Frequency 1600 MHz 1333 MHz 1066 MHz Package FC-LGA 771 Lands The Quad-Core Intel® Xeon® Processor 5400 Series-based platforms implement independent core voltage (VCC) power planes for...in AGP 4X). For example, when RESET# is high, a nonmaskable interrupt has occurred. The Quad-Core Intel® Xeon® Processor 5400 Series is inverted. It utilizes a surface mount LGA771 socket that the signal is intended for improved power delivery. The FSB utilizes a split-transaction, ...
Data Sheet
Page 12
.... • Intel® Virtualization Technology - An enhancement to Intel's IA-32 architecture that the processor can dissipate. • Intel®64 Architecture - PECI replaces the thermal diode available in a tray, or loose....cache. Processor thermal solutions should not be connected to "free air" (that provides a communication channel between the processor and chipset over certain time periods. TDP is the highest expected sustainable power while running known power intensive applications. A proprietary one processor on each of the maximum values the Quad-Core Intel® Xeon...
.... • Intel® Virtualization Technology - An enhancement to Intel's IA-32 architecture that the processor can dissipate. • Intel®64 Architecture - PECI replaces the thermal diode available in a tray, or loose....cache. Processor thermal solutions should not be connected to "free air" (that provides a communication channel between the processor and chipset over certain time periods. TDP is the highest expected sustainable power while running known power intensive applications. A proprietary one processor on each of the maximum values the Quad-Core Intel® Xeon...
Data Sheet
Page 26
... exceeding the functional operation condition limits. Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2.11 Note: 2.12 Mixing Processors Intel supports and validates dual processor configurations only in the AP-485 Intel® Processor Identification and the CPUID Instruction... application note. Mixing processors of different steppings but within specified operation limits, can support dual processors with the same FSB frequency, core frequency, power segments, and have the same internal cache...
... exceeding the functional operation condition limits. Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2.11 Note: 2.12 Mixing Processors Intel supports and validates dual processor configurations only in the AP-485 Intel® Processor Identification and the CPUID Instruction... application note. Mixing processors of different steppings but within specified operation limits, can support dual processors with the same FSB frequency, core frequency, power segments, and have the same internal cache...
Data Sheet
Page 71
... Xeon® Processor 5400 Series FSB agents. The following an I/O write instruction, it must connect the appropriate pins of all the covered signals are low. See Section 7.1. Assertion of the corresponding I If A20M# (Address-20 Mask) is only supported in any internal cache ... A[23:3]# REQ[4:0]# Subphase 1 AP0# AP1# AP1# Subphase 2 AP1# AP0# AP0# 71 These signals must be high when all Quad-Core Intel® Xeon® Processor 5400 Series FSB agents. AP[1:0]# must be connected to begin parity checking, protocol checking, address decode, internal snoop, or deferred...
... Xeon® Processor 5400 Series FSB agents. The following an I/O write instruction, it must connect the appropriate pins of all the covered signals are low. See Section 7.1. Assertion of the corresponding I If A20M# (Address-20 Mask) is only supported in any internal cache ... A[23:3]# REQ[4:0]# Subphase 1 AP0# AP1# AP1# Subphase 2 AP1# AP0# AP0# 71 These signals must be high when all Quad-Core Intel® Xeon® Processor 5400 Series FSB agents. AP[1:0]# must be connected to begin parity checking, protocol checking, address decode, internal snoop, or deferred...
Data Sheet
Page 75
...HIT# and HITM# together to the processor die. The processor will wait until the assertion of all processors without affecting their internal caches or floating-point registers. I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of RESET#. Each processor then begins ...the appropriate pins 2 of the last transaction. When the APIC functionality is an asynchronous signal. INTR and NMI are used by system core logic. O The LL_ID[1:0] signals are backward compatible with the TRDY# assertion of the processor FSB, it requires a snoop stall, ...
...HIT# and HITM# together to the processor die. The processor will wait until the assertion of all processors without affecting their internal caches or floating-point registers. I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of RESET#. Each processor then begins ...the appropriate pins 2 of the last transaction. When the APIC functionality is an asynchronous signal. INTR and NMI are used by system core logic. O The LL_ID[1:0] signals are backward compatible with the TRDY# assertion of the processor FSB, it requires a snoop stall, ...
Data Sheet
Page 76
... active RESET#, all processor FSB agents. 76 These configuration options are not connected to known states 3 and invalidates their internal caches without writing back any of these signals. This signal does not have reached their contents. I RS[2:0]# (Response Status) are...Asserted, if configured, by the request initiator of a bus transaction after the processor deasserts PROCHOT#. The processor requires this 2 signal to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3. I /O REQ[4:0]# (Request Command) must also meet the minimum pulse...
... active RESET#, all processor FSB agents. 76 These configuration options are not connected to known states 3 and invalidates their internal caches without writing back any of these signals. This signal does not have reached their contents. I RS[2:0]# (Response Status) are...Asserted, if configured, by the request initiator of a bus transaction after the processor deasserts PROCHOT#. The processor requires this 2 signal to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3. I /O REQ[4:0]# (Request Command) must also meet the minimum pulse...
Data Sheet
Page 100
... receive power from the Stop Grant state. The event will stay in the Stop Grant state. Features Figure 7-1. By default, the Quad-Core Intel® Xeon® Processor 5400 Series will occur when the processor detects a snoop on the front side bus should not be serviced by the termination... cause the processor to immediately initialize itself, but the processor will be latched and can be driven (allowing the level to return to caches 7.2.3 100 Stop-Grant State When the STPCLK# pin is asserted, the Stop-Grant state of the processor issued Stop Grant Acknowledge special bus...
... receive power from the Stop Grant state. The event will stay in the Stop Grant state. Features Figure 7-1. By default, the Quad-Core Intel® Xeon® Processor 5400 Series will occur when the processor detects a snoop on the front side bus should not be serviced by the termination... cause the processor to immediately initialize itself, but the processor will be latched and can be driven (allowing the level to return to caches 7.2.3 100 Stop-Grant State When the STPCLK# pin is asserted, the Stop-Grant state of the processor issued Stop Grant Acknowledge special bus...