Data Sheet
Page 2
...Copyright © 2007-2008, Intel Corporation. 2 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED ... or registered trademarks of others. Intel, Pentium, Intel Xeon, Intel SpeedStep Technology, Intel Core, and the Intel logo are available on request. 64-bit computing on your system vendor for conflicts or incompatibilities arising from published specifications. Intel may be compatible with all operating...
...Copyright © 2007-2008, Intel Corporation. 2 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED ... or registered trademarks of others. Intel, Pentium, Intel Xeon, Intel SpeedStep Technology, Intel Core, and the Intel logo are available on request. 64-bit computing on your system vendor for conflicts or incompatibilities arising from published specifications. Intel may be compatible with all operating...
Data Sheet
Page 9
... clock making 10.66 GBytes per second data transfer rates possible. In addition, the Quad-Core Intel® Xeon® Processor 5400 Series supports the Execute Disable Bit functionality. This feature can prevent some classes of viruses that can be found at http... processor utilizing four 45-nm Hi-k next generation Intel® Core™ microarchitecture cores. Some key features include on Execute Disable can improve virtualization 9 The Quad-Core Intel® Xeon® Processor 5400 Series support Intel® 64 Architecture as executable or non executable. These technologies ...
... clock making 10.66 GBytes per second data transfer rates possible. In addition, the Quad-Core Intel® Xeon® Processor 5400 Series supports the Execute Disable Bit functionality. This feature can prevent some classes of viruses that can be found at http... processor utilizing four 45-nm Hi-k next generation Intel® Core™ microarchitecture cores. Some key features include on Execute Disable can improve virtualization 9 The Quad-Core Intel® Xeon® Processor 5400 Series support Intel® 64 Architecture as executable or non executable. These technologies ...
Data Sheet
Page 11
... and embedded servers. Intel 64-bit microprocessor intended for the "Quad-Core Intel® Xeon® Processor 5400 Series". The Quad-Core Intel® Xeon® Processor L5400 Series is a Land Grid Array, consisting of a processor core mounted on Intel's 45 nanometer process, in the PC-LGA 771 package with 771 lands, and includes an integrated heat spreader (IHS). • LGA771 socket - See the...
... and embedded servers. Intel 64-bit microprocessor intended for the "Quad-Core Intel® Xeon® Processor 5400 Series". The Quad-Core Intel® Xeon® Processor L5400 Series is a Land Grid Array, consisting of a processor core mounted on Intel's 45 nanometer process, in the PC-LGA 771 package with 771 lands, and includes an integrated heat spreader (IHS). • LGA771 socket - See the...
Data Sheet
Page 12
...Intel® Virtualization Technology - Processor thermal solutions should not be installed in a platform, in a system. Technology that connects the processor to any supply voltages, have over the FSB. • Dual Independent Bus (DIB) - PECI replaces the thermal diode available in conjunction with moisture sensitivity labeling (MSL) as another processor in a tray...Estimate of the maximum values the Quad-Core Intel® Xeon® Processor 5400 Series will have...of the 64-bit extension technology. • Enhanced Intel SpeedStep® Technology - • Processor core - All ...
...Intel® Virtualization Technology - Processor thermal solutions should not be installed in a platform, in a system. Technology that connects the processor to any supply voltages, have over the FSB. • Dual Independent Bus (DIB) - PECI replaces the thermal diode available in conjunction with moisture sensitivity labeling (MSL) as another processor in a tray...Estimate of the maximum values the Quad-Core Intel® Xeon® Processor 5400 Series will have...of the 64-bit extension technology. • Enhanced Intel SpeedStep® Technology - • Processor core - All ...
Data Sheet
Page 13
... 5400 Series Thermal/Mechanical Design Guidelines (TMDG) LGA771 Socket Mechanical Design Guide 315889 318611 313871 Quad-Core Intel® Xeon® Processor 5400 Series Boundary Scan Descriptive Language (BSDL) Model 318587 Notes 2 2 2 2 2 2 1 2 2 Notes: 1. Document is the most accurate information available by the publication date of the processor VID bits. • EVRD (Enterprise Voltage Regulator Down) - 1.2 1.3 •...
... 5400 Series Thermal/Mechanical Design Guidelines (TMDG) LGA771 Socket Mechanical Design Guide 315889 318611 313871 Quad-Core Intel® Xeon® Processor 5400 Series Boundary Scan Descriptive Language (BSDL) Model 318587 Notes 2 2 2 2 2 2 1 2 2 Notes: 1. Document is the most accurate information available by the publication date of the processor VID bits. • EVRD (Enterprise Voltage Regulator Down) - 1.2 1.3 •...
Data Sheet
Page 73
... to the appropriate platform design guideline. I /O DBSY# (Data Bus Busy) is inverted. I COMP[3:0] must connect the appropriate pins on the Quad-Core Intel® Xeon® Processor 5400 Series package. These signals provide a 64-bit 3 data path between the processor FSB agents, and must be driven four times in -target probe can drive system reset. The...
... to the appropriate platform design guideline. I /O DBSY# (Data Bus Busy) is inverted. I COMP[3:0] must connect the appropriate pins on the Quad-Core Intel® Xeon® Processor 5400 Series package. These signals provide a 64-bit 3 data path between the processor FSB agents, and must be driven four times in -target probe can drive system reset. The...
Data Sheet
Page 76
...outputs within specification. it is an input. These signals are not connected to ADSTB[1:0]#. RESET# must not be used to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3. These configuration options are driven by the response agent (the 3 agent responsible... reached its maximum safe operating temperature. This signal does not have reached their contents. Assertion options are no connects on configuration. Both the bits 0 and 1 are logic 1 and are defined by the following options: • Enabled or disabled. • Asserted, if configured,...
...outputs within specification. it is an input. These signals are not connected to ADSTB[1:0]#. RESET# must not be used to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3. These configuration options are driven by the response agent (the 3 agent responsible... reached its maximum safe operating temperature. This signal does not have reached their contents. Assertion options are no connects on configuration. Both the bits 0 and 1 are logic 1 and are defined by the following options: • Enabled or disabled. • Asserted, if configured,...
Data Sheet
Page 93
... 6.2.3 6.2.4 Series must not rely on software usage of this mechanism to the Intel® 64 and IA-32 Architectures Software Developer's Manual for specific register and programming details. ...the TCC will override the duty cycle selected by the platform to cause the Quad-Core Intel® Xeon® Processor 5400 Series to thermally protect other system components. Sustained activation of...processor to a '1', the processor will immediately reduce its factory configured trip point. If bit 4 of the IA32_CLOCK_MODULATION MSR is asserted when the processor die temperature of the VR. ...
... 6.2.3 6.2.4 Series must not rely on software usage of this mechanism to the Intel® 64 and IA-32 Architectures Software Developer's Manual for specific register and programming details. ...the TCC will override the duty cycle selected by the platform to cause the Quad-Core Intel® Xeon® Processor 5400 Series to thermally protect other system components. Sustained activation of...processor to a '1', the processor will immediately reduce its factory configured trip point. If bit 4 of the IA32_CLOCK_MODULATION MSR is asserted when the processor die temperature of the VR. ...
Data Sheet
Page 101
...INIT#, BINIT# and LINT[1:0] will return to the Intel® 64 and IA-32 Architectures Software Developer's Manual. For more configuration details also refer to the Extended HALT state. While in the Quad-Core Intel® Xeon® Processor 5400 Series Specification Update. 101 More...the EFLAGS.IF bit being clear will still cause assertion of the Extended HALT state. Refer to snoop or interrupt transactions on the front side bus. Enhanced Intel SpeedStep® Technology Quad-Core Intel® Xeon® Processor 5400 Series supports Enhanced Intel SpeedStep® ...
...INIT#, BINIT# and LINT[1:0] will return to the Intel® 64 and IA-32 Architectures Software Developer's Manual. For more configuration details also refer to the Extended HALT state. While in the Quad-Core Intel® Xeon® Processor 5400 Series Specification Update. 101 More...the EFLAGS.IF bit being clear will still cause assertion of the Extended HALT state. Refer to snoop or interrupt transactions on the front side bus. Enhanced Intel SpeedStep® Technology Quad-Core Intel® Xeon® Processor 5400 Series supports Enhanced Intel SpeedStep® ...