English Product Guide
Page 4
...Kilobyte (1024 bytes) Megabyte (1,048,576 bytes) Megabit (1,048,576 bits) Megahertz (one million hertz) Box Contents • Intel® Desktop Board • NVIDIA* GeForce* 6200 LE Graphics Card • I/O shield • One ATA-66/100 cable • Four Serial ATA cables • Two Serial ATA... power cables • One diskette drive cable • Intel® Express Installer CD-ROM • Floppy disk with RAID driver • Back panel audio ...
...Kilobyte (1024 bytes) Megabyte (1,048,576 bytes) Megabit (1,048,576 bits) Megahertz (one million hertz) Box Contents • Intel® Desktop Board • NVIDIA* GeForce* 6200 LE Graphics Card • I/O shield • One ATA-66/100 cable • Four Serial ATA cables • Two Serial ATA... power cables • One diskette drive cable • Intel® Express Installer CD-ROM • Floppy disk with RAID driver • Back panel audio ...
Data Sheet
Page 7
...(FEE0_0000h-FEEF_FFFFh 165 9.3.4 High BIOS Area 165 9.3.5 PCI Express* Configuration Address Space 165 9.3.6 PCI Express* Graphics Attach 166 9.3.7 AGP DRAM Graphics Aperture 166 9.4 System Management Mode (SMM 167 9.4.1 SMM Space Definition 167 9.4.2 SMM Space Restrictions 168 ...10.3.3 Suspend to RAM and Resume 181 10.3.4 DDR2 On-Die Termination 181 10.3.5 DDR2 Off-Chip Driver Impedance Calibration 181 10.4 PCI Express* ...182 10.4.1 Transaction Layer 182 10.4.2 Data Link Layer 182 ...193 12.1 Ballout...193 12.2 Package Information 219 Intel® 82925X/82925XE MCH Datasheet 7
...(FEE0_0000h-FEEF_FFFFh 165 9.3.4 High BIOS Area 165 9.3.5 PCI Express* Configuration Address Space 165 9.3.6 PCI Express* Graphics Attach 166 9.3.7 AGP DRAM Graphics Aperture 166 9.4 System Management Mode (SMM 167 9.4.1 SMM Space Definition 167 9.4.2 SMM Space Restrictions 168 ...10.3.3 Suspend to RAM and Resume 181 10.3.4 DDR2 On-Die Termination 181 10.3.5 DDR2 Off-Chip Driver Impedance Calibration 181 10.4 PCI Express* ...182 10.4.1 Transaction Layer 182 10.4.2 Data Link Layer 182 ...193 12.1 Ballout...193 12.2 Package Information 219 Intel® 82925X/82925XE MCH Datasheet 7
Data Sheet
Page 12
...) ⎯ GTL+ bus driver with integrated GTL ⎯ SPD (Serial Presence Detect) scheme for termination resistors DIMM detection support ⎯ Supports a Cache Line Size of 64 bytes ⎯ Suspend-to-RAM support using CKE ⎯ Supports Intel Pentium® 4 processors with ...9135; Supports configurations defined in the Intel® EM64T Φ JEDEC DDR2 DIMM specification only DMI Interface PCI Express Graphics Interface ⎯ A chip-to-chip connection interface to Intel® ⎯ One...
...) ⎯ GTL+ bus driver with integrated GTL ⎯ SPD (Serial Presence Detect) scheme for termination resistors DIMM detection support ⎯ Supports a Cache Line Size of 64 bytes ⎯ Suspend-to-RAM support using CKE ⎯ Supports Intel Pentium® 4 processors with ...9135; Supports configurations defined in the Intel® EM64T Φ JEDEC DDR2 DIMM specification only DMI Interface PCI Express Graphics Interface ⎯ A chip-to-chip connection interface to Intel® ⎯ One...
Data Sheet
Page 28
...DRAM Over Current Detection (OCD) driver A compensation I Buffer Slew Rate Input: Slew Rate Characterization buffer input for DMI current compensation. A PCI Express* x16 Graphics Port Signals Unless otherwise specified, PCI Express Graphics signals are AC coupled, so ...= Normal operation 28 Intel® 82925X/82925XE MCH Datasheet A O Buffer Slew Rate Output: Slew Rate Characterization buffer output for X and Y orientation A I SDRAM Reference Voltage: Reference voltage inputs for DMI current compensation. EXP_TXP1... PCI Express Graphics Input Current Compensation Note...
...DRAM Over Current Detection (OCD) driver A compensation I Buffer Slew Rate Input: Slew Rate Characterization buffer input for DMI current compensation. A PCI Express* x16 Graphics Port Signals Unless otherwise specified, PCI Express Graphics signals are AC coupled, so ...= Normal operation 28 Intel® 82925X/82925XE MCH Datasheet A O Buffer Slew Rate Output: Slew Rate Characterization buffer output for X and Y orientation A I SDRAM Reference Voltage: Reference voltage inputs for DMI current compensation. EXP_TXP1... PCI Express Graphics Input Current Compensation Note...
Data Sheet
Page 76
...): 1 = The MCH generates an SCI DMI special cycle when the DRAM controller detects a single bit error. 0 = Reporting of BIOS and graphics drivers. When an error flag is for the convenience of this bit must be disabled. 82925XE MCH Reserved 0 R/W 0b 82925X MCH SCI on Multiple-... enabled in the ERRSTS register, it detects a multiple-bit error reported by the DRAM controller. 0 = Reporting of data storage. 00000000 h 76 Intel® 82925X/82925XE MCH Datasheet Bit Access & Default Description 31:0 R/W Scratchpad Data: 1 DWord of this bit must be enabled. Host Bridge/DRAM...
...): 1 = The MCH generates an SCI DMI special cycle when the DRAM controller detects a single bit error. 0 = Reporting of BIOS and graphics drivers. When an error flag is for the convenience of this bit must be disabled. 82925XE MCH Reserved 0 R/W 0b 82925X MCH SCI on Multiple-... enabled in the ERRSTS register, it detects a multiple-bit error reported by the DRAM controller. 0 = Reporting of data storage. 00000000 h 76 Intel® 82925X/82925XE MCH Datasheet Bit Access & Default Description 31:0 R/W Scratchpad Data: 1 DWord of this bit must be enabled. Host Bridge/DRAM...
Data Sheet
Page 125
...Express* Graphics Bridge Registers (D1:F0) R 8.1.20 INTRLINE1-Interrupt Line (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 3Ch 00h R/W 8 bits This register contains interrupt line routing information. rather device drivers and... operating systems use this device uses. Bit Access & Default Description 7:0 RO Interrupt Pin: As a single function device, the PCI Express* device specifies 01h INTA as it to determine priority and vector information. POST software writes the routing information into this register as its interrupt pin. 01h = INTA Intel...
...Express* Graphics Bridge Registers (D1:F0) R 8.1.20 INTRLINE1-Interrupt Line (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 3Ch 00h R/W 8 bits This register contains interrupt line routing information. rather device drivers and... operating systems use this device uses. Bit Access & Default Description 7:0 RO Interrupt Pin: As a single function device, the PCI Express* device specifies 01h INTA as it to determine priority and vector information. POST software writes the routing information into this register as its interrupt pin. 01h = INTA Intel...
Data Sheet
Page 128
... states are supported. Pointer to Next Capability: This field contains a pointer to 0. Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.23 PM_CAPID1-Power Management Capabilities (D1:F0) PCI Device: Address Offset... Capability ID: Value of this device is NOT required before generic class device driver is to indicate that this linked list item (capability structure) as being for... Hardwired to 0 to the PCI Power Management 1.1 specification for PCI Power Management registers. 128 Intel® 82925X/82925XE MCH Datasheet If MSICH (CAPL[0] @ 7Fh) is 1, then the next...
... states are supported. Pointer to Next Capability: This field contains a pointer to 0. Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.23 PM_CAPID1-Power Management Capabilities (D1:F0) PCI Device: Address Offset... Capability ID: Value of this device is NOT required before generic class device driver is to indicate that this linked list item (capability structure) as being for... Hardwired to 0 to the PCI Power Management 1.1 specification for PCI Power Management registers. 128 Intel® 82925X/82925XE MCH Datasheet If MSICH (CAPL[0] @ 7Fh) is 1, then the next...
Data Sheet
Page 132
...receive PME or HotPlug messages. INTA will not be generated and INTA Status (PCISTS1[3]) will be set. 132 Intel® 82925X/82925XE MCH Datasheet If all of those messages is prohibited from doing so. This number will be...Reserved 0 R/W MSI Enable (MSIEN) Controls the ability of messages allocated to be serviced, the device must be serviced. Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.28 MC-Message Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 ... them must not generate the same message again until the driver services the earlier one.
...receive PME or HotPlug messages. INTA will not be generated and INTA Status (PCISTS1[3]) will be set. 132 Intel® 82925X/82925XE MCH Datasheet If all of those messages is prohibited from doing so. This number will be...Reserved 0 R/W MSI Enable (MSIEN) Controls the ability of messages allocated to be serviced, the device must be serviced. Host-PCI Express* Graphics Bridge Registers (D1:F0) R 8.1.28 MC-Message Control (D1:F0) PCI Device: Address Offset: Default Value: Access: Size: 1 ... them must not generate the same message again until the driver services the earlier one.
Data Sheet
Page 182
...Physical Layer The Physical Layer includes all existing applications and drivers operate unchanged. The PCI Express architecture is considered a Fatal Error. TLPs are used to -parallel conversion, PLL(s), and impedance matching circuitry. 182 Intel® 82925X/82925XE MCH Datasheet Compatibility with the PCI addressing.... The PCI Express configuration uses standard mechanisms as certain types of a PCI Express root complex. Note: The PCI Express graphics port will not log or identify the second malformed packet. However, the 1st malformed TLP is logged, and is specified ...
...Physical Layer The Physical Layer includes all existing applications and drivers operate unchanged. The PCI Express architecture is considered a Fatal Error. TLPs are used to -parallel conversion, PLL(s), and impedance matching circuitry. 182 Intel® 82925X/82925XE MCH Datasheet Compatibility with the PCI addressing.... The PCI Express configuration uses standard mechanisms as certain types of a PCI Express root complex. Note: The PCI Express graphics port will not log or identify the second malformed packet. However, the 1st malformed TLP is logged, and is specified ...