Data Sheet
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Contents Revision Historyxix 1 AMD-K6®-2 Processor 1 1.1 Super7™ Platform Initiative 3 Super7™ Platform Enhancements 3 Super7™ Platform Advantages 4 2 Internal Architecture 5 2.1 Introduction 5 2.2 AMD-K6®-2 Processor Microarchitecture Overview 5 Enhanced RISC86® Microarchitecture 6 2.3 Cache, Instruction Prefetch, and Predecode Bits 9 Cache 9 Prefetching 10 Predecode Bits 10 2.4 Instruction Fetch and Decode 11...
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Contents Revision Historyxix 1 AMD-K6®-2 Processor 1 1.1 Super7™ Platform Initiative 3 Super7™ Platform Enhancements 3 Super7™ Platform Advantages 4 2 Internal Architecture 5 2.1 Introduction 5 2.2 AMD-K6®-2 Processor Microarchitecture Overview 5 Enhanced RISC86® Microarchitecture 6 2.3 Cache, Instruction Prefetch, and Predecode Bits 9 Cache 9 Prefetching 10 Predecode Bits 10 2.4 Instruction Fetch and Decode 11...
Data Sheet
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... (EFER) -Model 8/[F:8] . 50 Write Handling Control Register (WHCR)-Model 8/[F:8] . . 51 UC/WC Cacheability Control Register (UWCCR)52 Processor State Observability Register (PSOR 53 Page Flush/Invalidate Register (PFIR 53 3.3 Instructions Supported by the AMD-K6®-2 Processor . . . . . 54 4 Signal Descriptions 83 4.1 Signal Terminology 83 4.2 A20M# (Address Bit 20 Mask 85 4.3 A[31:3] (Address Bus 86...
... (EFER) -Model 8/[F:8] . 50 Write Handling Control Register (WHCR)-Model 8/[F:8] . . 51 UC/WC Cacheability Control Register (UWCCR)52 Processor State Observability Register (PSOR 53 Page Flush/Invalidate Register (PFIR 53 3.3 Instructions Supported by the AMD-K6®-2 Processor . . . . . 54 4 Signal Descriptions 83 4.1 Signal Terminology 83 4.2 A20M# (Address Bit 20 Mask 85 4.3 A[31:3] (Address Bus 86...
Data Sheet
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Contents 4.33 LOCK# (Bus Lock 110 4.34 M/IO# (Memory or I/O 111 4.35 NA# (Next Address 112 4.36 NMI (Non-Maskable Interrupt 112 4.37 ...
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Contents 4.33 LOCK# (Bus Lock 110 4.34 M/IO# (Memory or I/O 111 4.35 NA# (Next Address 112 4.36 NMI (Non-Maskable Interrupt 112 4.37 ...
Data Sheet
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 AHOLD-Initiated Inquire Hit to Modified Line 152 AHOLD Restriction 154 Bus Backoff (BOFF 156 Locked Cycles 158 ... 6.1 Signals Sampled During the Falling Transition of RESET 173 FLUSH 173 BF[2:0 173 BRDYC 173 6.2 RESET Requirements 174 6.3 State of Processor After RESET 174 Output Signals 174 Registers 174 6.4 State of Processor After INIT 177 7 Cache Organization 179 7.1 MESI States in the Data Cache 180 7.2 Predecode Bits 180 7.3 Cache Operation 181 Cache...
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 AHOLD-Initiated Inquire Hit to Modified Line 152 AHOLD Restriction 154 Bus Backoff (BOFF 156 Locked Cycles 158 ... 6.1 Signals Sampled During the Falling Transition of RESET 173 FLUSH 173 BF[2:0 173 BRDYC 173 6.2 RESET Requirements 174 6.3 State of Processor After RESET 174 Output Signals 174 Registers 174 6.4 State of Processor After INIT 177 7 Cache Organization 179 7.1 MESI States in the Data Cache 180 7.2 Predecode Bits 180 7.3 Cache Operation 181 Cache...
Data Sheet
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Contents WBINVD and INVD 196 Cache-Line Replacement 196 Cache Snooping 198 7.11 Writethrough versus Writeback Coherency States 199 7.12 A20M# Masking of ...
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Contents WBINVD and INVD 196 Cache-Line Replacement 196 Cache Snooping 198 7.11 Writethrough versus Writeback Coherency States 199 7.12 A20M# Masking of ...
Data Sheet
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 12 Clock Control 243 12.1 Halt State 244 Enter Halt State 244 Exit Halt State 244 12.2 Stop ... Note 265 15.4 I/O Buffer AC and DC Characteristics 265 16 Signal Switching Characteristics 267 16.1 CLK Switching Characteristics 267 16.2 Clock Switching Characteristics for 100-MHz Bus Operation 268 16.3 Clock Switching Characteristics for 66-MHz Bus Operation 268 16.4 Valid Delay, Float, Setup, and Hold Timings 269 viii Contents
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 12 Clock Control 243 12.1 Halt State 244 Enter Halt State 244 Exit Halt State 244 12.2 Stop ... Note 265 15.4 I/O Buffer AC and DC Characteristics 265 16 Signal Switching Characteristics 267 16.1 CLK Switching Characteristics 267 16.2 Clock Switching Characteristics for 100-MHz Bus Operation 268 16.3 Clock Switching Characteristics for 66-MHz Bus Operation 268 16.4 Valid Delay, Float, Setup, and Hold Timings 269 viii Contents
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 16.5 Output Delay Timings for 100-MHz Bus Operation 270 16.6 Input Setup and Hold Timings for 100-MHz Bus Operation 272 16.7 Output Delay Timings for 66-MHz Bus Operation 274 16.8 Input Setup and Hold Timings for 66-MHz Bus Operation 276 16.9 RESET and...
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 16.5 Output Delay Timings for 100-MHz Bus Operation 270 16.6 Input Setup and Hold Timings for 100-MHz Bus Operation 272 16.7 Output Delay Timings for 66-MHz Bus Operation 274 16.8 Input Setup and Hold Timings for 66-MHz Bus Operation 276 16.9 RESET and...
Data Sheet
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... Register 1 (CR1 33 Figure 25. Test Register 12 (TR12 38 Figure 33. 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet List of Figures xi The Instruction Buffer 11 AMD-K6®-2 Processor Decode Logic 12 AMD-K6®-2 Processor Scheduler 15 Figure 6. Packed Decimal Data Register 28 Figure 16. Control Register 4 (CR4 32 Figure 22. Write...
... Register 1 (CR1 33 Figure 25. Test Register 12 (TR12 38 Figure 33. 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet List of Figures xi The Instruction Buffer 11 AMD-K6®-2 Processor Decode Logic 12 AMD-K6®-2 Processor Scheduler 15 Figure 6. Packed Decimal Data Register 28 Figure 16. Control Register 4 (CR4 32 Figure 22. Write...
Data Sheet
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... Figure 38. Page Table Entry (PTE 46 Figure 44. Write Handling Control Register (WHCR)-Model 8/[F:8] . . 52 Figure 49. Processor State Observability Register (PSOR 53 Figure 51. Bus State Machine Diagram 129 Figure 55. Burst Writeback due to Shared or Exclusive Line ... Mechanism 44 Figure 41. Application Segment Descriptor 47 Figure 45. Misaligned Single-Transfer Memory Read and Write 135 Figure 57. AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Figure 37. Page Flush/Invalidate Register (PFIR 53 Figure 52. System Segment Descriptor 48...
... Figure 38. Page Table Entry (PTE 46 Figure 44. Write Handling Control Register (WHCR)-Model 8/[F:8] . . 52 Figure 49. Processor State Observability Register (PSOR 53 Figure 51. Bus State Machine Diagram 129 Figure 55. Burst Writeback due to Shared or Exclusive Line ... Mechanism 44 Figure 41. Application Segment Descriptor 47 Figure 45. Misaligned Single-Transfer Memory Read and Write 135 Figure 57. AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Figure 37. Page Flush/Invalidate Register (PFIR 53 Figure 52. System Segment Descriptor 48...
Data Sheet
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... Register (PFIR)- CLK Waveform 269 Figure 96. Input Setup and Hold Timing 282 Figure 100. Thermal Model 288 Figure 105. Processor Heat Dissipation Path 290 Figure 107. Model 8/[7:0 187 Figure 80. Model 8/[F:8 188 Figure 81. Cache Organization 179 Figure 78.... Logic for Supporting Floating-Point Exceptions. . . 208 Figure 85. Voltage Regulator Placement 291 xiii 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet List of Figures Figure 75. K6STD Pulldown V/I Curves 265 Figure 95. Stop Grant and Stop Clock Modes, Part...
... Register (PFIR)- CLK Waveform 269 Figure 96. Input Setup and Hold Timing 282 Figure 100. Thermal Model 288 Figure 105. Processor Heat Dissipation Path 290 Figure 107. Model 8/[7:0 187 Figure 80. Model 8/[F:8 188 Figure 81. Cache Organization 179 Figure 78.... Logic for Supporting Floating-Point Exceptions. . . 208 Figure 85. Voltage Regulator Placement 291 xiii 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet List of Figures Figure 75. K6STD Pulldown V/I Curves 265 Figure 95. Stop Grant and Stop Clock Modes, Part...
Data Sheet
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Airflow for a Heatsink with Fan 292 Figure 110. Airflow Path in a Dual-Fan System 293 Figure 111. Airflow Path in an ATX Form-Factor System 293 Figure 112. AMD-K6®-2 Processor Pin-Side View 296 Figure 114. 321-Pin Staggered CPGA Package Specification 300 xiv List of Figures AMD-K6®-2 Processor Top-Side View 295 Figure 113. AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Figure 109.
Airflow for a Heatsink with Fan 292 Figure 110. Airflow Path in a Dual-Fan System 293 Figure 111. Airflow Path in an ATX Form-Factor System 293 Figure 112. AMD-K6®-2 Processor Pin-Side View 296 Figure 114. 321-Pin Staggered CPGA Package Specification 300 xiv List of Figures AMD-K6®-2 Processor Top-Side View 295 Figure 113. AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Figure 109.
Data Sheet
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...10. Table 13. Table 17. Table 22. Table 26. Table 29. Execution Latency and Throughput of Exceptions and Interrupts 49 AMD-K6®-2 Processor Model 8/[F:8] MSRs 50 Extended Feature Enable Register (EFER)- Model 8[7:0]Definition 39 SYSCALL/SYSRET Target Address Register (STAR) Definition 40... Units . . . . . 16 General-Purpose Registers 22 General-Purpose Register Doubleword, Word, and Byte Names 23 Segment Registers 24 AMD-K6®-2 Processor Model 8/[7:0] MSRs 37 Extended Feature Enable Register (EFER) - Table 9. Table 21. Table 25. Table 27. Table 30. Table 34...
...10. Table 13. Table 17. Table 22. Table 26. Table 29. Execution Latency and Throughput of Exceptions and Interrupts 49 AMD-K6®-2 Processor Model 8/[F:8] MSRs 50 Extended Feature Enable Register (EFER)- Model 8[7:0]Definition 39 SYSCALL/SYSRET Target Address Register (STAR) Definition 40... Units . . . . . 16 General-Purpose Registers 22 General-Purpose Register Doubleword, Word, and Byte Names 23 Segment Registers 24 AMD-K6®-2 Processor Model 8/[7:0] MSRs 37 Extended Feature Enable Register (EFER) - Table 9. Table 21. Table 25. Table 27. Table 30. Table 34...
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... Switching Characteristics for 100-MHz Bus Operation . 268 CLK Switching Characteristics for 66-MHz Bus Operation . . 268 Output Delay Timings for 100-MHz Bus Operation 270 Input Setup and Hold Timings for 100-MHz Bus Operation . 272 Output Delay Timings for 66-MHz Bus Operation 274 Input ...MHz 280 Package Thermal Specification for OPN Suffixes AHX, AFQ, and AFR 285 xvi List of Tables Table 43. Table 47. Table 49. Table 57. Table 59. Table 63. Table 66. Table 68. Table 69. Table 41. Table 67. Table 70. Table 48. Table 51. Table 61. Table 65. AMD-K6®-2 Processor...
... Switching Characteristics for 100-MHz Bus Operation . 268 CLK Switching Characteristics for 66-MHz Bus Operation . . 268 Output Delay Timings for 100-MHz Bus Operation 270 Input Setup and Hold Timings for 100-MHz Bus Operation . 272 Output Delay Timings for 66-MHz Bus Operation 274 Input ...MHz 280 Package Thermal Specification for OPN Suffixes AHX, AFQ, and AFR 285 xvi List of Tables Table 43. Table 47. Table 49. Table 57. Table 59. Table 63. Table 66. Table 68. Table 69. Table 41. Table 67. Table 70. Table 48. Table 51. Table 61. Table 65. AMD-K6®-2 Processor...
Data Sheet
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Package Thermal Specification for OPN Suffixes AGR, AFX, and 400AFR 287 321-Pin Staggered CPGA Package Specification 299 Valid Ordering Part Number Combinations 301 List of Tables xvii Table 73. 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 72. Table 74.
Package Thermal Specification for OPN Suffixes AGR, AFX, and 400AFR 287 321-Pin Staggered CPGA Package Specification 299 Valid Ordering Part Number Combinations 301 List of Tables xvii Table 73. 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 72. Table 74.
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 xviii List of Tables
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 xviii List of Tables
Data Sheet
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Revision History Date Feb... Organization" and added Figure 82,"Page Flush/Invalidate Register (PFIR)-MSR C000_0088h," and PFIR's bit descriptions. Added 500 MHz specifications. Added definition of Boundary Scan Register (BSR) for Model 8/[F:8] in I Table 55, "Typical and Maximum ...OPN Suffixes AHX, AFQ, and AFR," on page 229. Updated Chapter 21, "Ordering Information". Added 533 MHz specifications. Changed Stop Grant, Halt, and Stop Clock power specifications in Table 48 on page 285. Revised Table...
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Revision History Date Feb... Organization" and added Figure 82,"Page Flush/Invalidate Register (PFIR)-MSR C000_0088h," and PFIR's bit descriptions. Added 500 MHz specifications. Added definition of Boundary Scan Register (BSR) for Model 8/[F:8] in I Table 55, "Typical and Maximum ...OPN Suffixes AHX, AFQ, and AFR," on page 229. Updated Chapter 21, "Ordering Information". Added 533 MHz specifications. Changed Stop Grant, Halt, and Stop Clock power specifications in Table 48 on page 285. Revised Table...
Data Sheet
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 xx Revision History
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 xx Revision History
Data Sheet
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...superscalar instruction execution s Compatible with additional 20-Kbytes of x86 software. Chapter 1 AMD-K6®-2 Processor 1 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 1 AMD-K6®-2 Processor s Advanced 6-Issue RISC86® Superscalar Microarchitecture x Ten parallel specialized execution units ... Level-One (L1) Cache x 32-Kbyte instruction cache with Super7™ platform x Leverages high-speed 100-MHz processor bus x Accelerated Graphic Port (AGP) support s High-Performance IEEE 754-Compatible and 854-Compatible Floating-Point Unit...
...superscalar instruction execution s Compatible with additional 20-Kbytes of x86 software. Chapter 1 AMD-K6®-2 Processor 1 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 1 AMD-K6®-2 Processor s Advanced 6-Issue RISC86® Superscalar Microarchitecture x Ten parallel specialized execution units ... Level-One (L1) Cache x 32-Kbyte instruction cache with Super7™ platform x Leverages high-speed 100-MHz processor bus x Accelerated Graphic Port (AGP) support s High-Performance IEEE 754-Compatible and 854-Compatible Floating-Point Unit...
Data Sheet
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..., data forwarding, speculative execution, and register renaming. technology. technology. These design techniques enable the AMD-K6-2 processor to the x86 processor architecture that implements state-of predecode cache), a powerful IEEE 754-compatible and 854-compatible floating-point...-standard multimedia execution unit for executing MMX™ instructions. The AMD-K6-2 processor is x86 binary code compatible. AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 The AMD-K6-2 processor is the first to incorporate 3DNow!™ technology, a significant ...
..., data forwarding, speculative execution, and register renaming. technology. technology. These design techniques enable the AMD-K6-2 processor to the x86 processor architecture that implements state-of predecode cache), a powerful IEEE 754-compatible and 854-compatible floating-point...-standard multimedia execution unit for executing MMX™ instructions. The AMD-K6-2 processor is x86 binary code compatible. AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 The AMD-K6-2 processor is the first to incorporate 3DNow!™ technology, a significant ...
Data Sheet
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...Enhancements The Super7 platform has the following enhancements: s 100-MHz processor bus-The AMD-K6-2 processor supports a 100-MHz, 800 Mbyte/second frontside bus to provide a high-speed interface to 550 MHz and beyond. The 100-MHz interface to the frontside Level 2 (L2) cache and...for more than 120 million x86 microprocessors, including more information. 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet robust Socket 7 platform. Currently, over the 66-MHz Socket 7 interface-resulting in order to maintain the competitive vitality of the Socket 7 ...
...Enhancements The Super7 platform has the following enhancements: s 100-MHz processor bus-The AMD-K6-2 processor supports a 100-MHz, 800 Mbyte/second frontside bus to provide a high-speed interface to 550 MHz and beyond. The 100-MHz interface to the frontside Level 2 (L2) cache and...for more than 120 million x86 microprocessors, including more information. 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet robust Socket 7 platform. Currently, over the 66-MHz Socket 7 interface-resulting in order to maintain the competitive vitality of the Socket 7 ...