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Popular AMD AMD-K6-2/450 Manual Pages
Design Guide - Page 9
...Table 16. Summary by Model of MSR Differences within the AMD-K6™ Family 15
Table 9. Write Ordering and Performance Settings for UWCCR Register. . . . 32
Table 17. Processor-to-Bus Clock Ratios (Models 8/[F:8] and 9) . . 35
ix Extended Feature Enable Register (EFER) Definition (Models 7 and 8/[7:0 18
Table 11. Model-Specific Registers Supported by Models 7 and 8/[7:0 17
Table...
Design Guide - Page 14
...-III AMD-K6-IIIE+
Model/ Process (in the Write Handling Control Register (WHCR) and Extended Feature Enable Register (EFER)
differently from the models 7 and 8/[7:0]. 3. Low-power versions implement one additional register to determine specific function support. Table 1.
Table 1 shows the features of each member. Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide...
Design Guide - Page 15
AMD-K6™-2 Processor
Model 8/[7:0] Model 8/[F:8]
Some important features supported by the AMD-K6-2 processor include the 3DNow!™ instruction set and a 100-MHz processor bus. s Model 8/[7:0] implements the same six MSRs as a desktop product. Model 8/[F:8] is any of eight possible model/steppings-models 8/8, 8/9, 8/A, 8/B, 8/C, 8/D, 8/E, or 8/F. s Model 8/[F:8] implements the same ...
Design Guide - Page 16
... set and a 100MHz processor bus, the AMD-K6-2E+ processor contains a 128Kbyte backside L2 cache. Model 8/[F:8] is any of ten MSRs. instruction set and a 100-MHz processor bus. s Low-power versions of twelve MSRs.
4
Processor Models and Steppings Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0-November 2000
AMD-K6™-2E Embedded Processor
Model...
Design Guide - Page 17
...Information Embedded AMD-K6™ Processors BIOS Design Guide
AMD-K6™-III Processor
Model 9/[3:0]
In addition to supporting the 3DNow! It also supports the 3DNow! s Model D/[3:0] implements the same ten MSRs as the Model 8/[F:8].
s Model 9/[3:0] implements the same ten MSRs as the Model 8/[F:8].
instruction set and a 100MHz processor bus, the AMD-K6-III processor contains...
Design Guide - Page 24
...
Figure 1. Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0-November 2000
Check for CPUID instruction support
CPUID instruction
No
supported
No CPUID instruction-Use other CPU brands
Store returned Standard Function Feature bits and
Processor Signature; technology information for the
processor
Tune software to gather AMD PowerNow! Yes Execute CPUID...
Design Guide - Page 50
... by the RDMSR and WRMSR instruction. In addition, the processor also contains a 256-Kbyte, 4-way set associativity. Model-Specific Registers Supported by the implementation of ECX selects the MSR to Model 8/[F:8].
The AMD-K6-III processor contains a split Level-1 (L1) 64-Kbyte writeback cache organized as a separate 32-Kbyte instruction cache and a 32-Kbyte data cache with two-way...
Design Guide - Page 69
... or speed of 3DNow! more powerful extensions for hardware and software to return a complete picture about the processor, including the vendor, model number, revision (stepping), features, cache organization, and processor name. 23913A/0-November 2000
Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide
Embedded AMD Processor Recognition
The CPUID instruction provides...
Design Guide - Page 70
... in future generations of the CPUID instruction. Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0-November 2000
s Standard functions provide a simple method for a user program to detect and handle illegal instruction exceptions. If an exception occurs, the processor does not have CPUID support.
The CPUID sample code described on page 71 contains...
Design Guide - Page 75
....
1
1
14 MCA (Machine Check Architecture) Machine check architecture is present on all AMD processors
0
0
22
AMD Multimedia Instruction Extensions
AMD additions to the original MMX™ instruction set
are returned in the
5 Model-Specific Registers (with processor, and the RDMSR and WRMSR instructions 1
1
RDMSR and WRMSR)
are supported.
6 PAE (Page Address Extensions)
Page...
Design Guide - Page 76
... AMD-K6™ Processors BIOS Design Guide
23913A/0-November 2000
Table 30. Attempting to determine if the processor executes the MMX technology instructions. "Appendix A" on page 71, and "Appendix B" on page 81 contain details on bit values. 2. See the AMD Extensions to the 3DNow!™ and MMX™ Instructions Sets Manual, order#
22466. instructions are supported.3
31 AMD...
Design Guide - Page 77
... to 1, MMX technology is at least 1, execute CPUID function 1, which returns the processor vendor string and the highest standard function supported. Save the vendor string for extended functions.
7.
Vendor Check
9. 23913A/0-November 2000
Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide
Detection Algorithm for Determining Instruction Set Support
To simplify...
Design Guide - Page 78
... the ASCII NULL character (00h). Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0-November 2000
3DNow! Figure 30 shows the contents returned in the EAX register.
31
12 11 8 7 4 3 0
Reserved
Generation/Family
11-8
Model
7-4
Stepping
3-0
Figure 30. Extensions Test
AMD Multimedia Instruction Extensions Test
10. To simplify the display routines...
Design Guide - Page 83
... AMD-K6™ Processors BIOS Design Guide
Appendix A
CPUID
mnemonic
opcode description
CPUID
0F A2h Identify the processor and its feature set
Privilege:
none
Registers Affected: EAX, EBX, ECX, EDX
Flags Affected:
none
Exceptions Generated: none
The CPUID instruction is an application-level instruction that the CPUID instruction is supported. In general, all AMD processors support...
Design Guide - Page 95
..., 65, 72
B
BDC Field 56 BF Field 34 BF Signals 34 BIOS Considerations 6
BIOS boot strings 66 bus divisor control 56 cache invalidation 19 cache testing 7 CPU speed detection 6 CPUID instruction 6 displaying processor name 66 EFER recommended setting 26 model-specific registers (MSRs 6 shadowed 70 SMM issues 7 voltage ID control 56 write allocate limit 20 write allocate mechanisms...
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