Intel E5405 - Cpu Xeon Quad Core 2.00Ghz Fsb1333Mhz 12M Lga771 Tray Support and Manuals
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Popular Intel E5405 Manual Pages
Specification Update - Page 2
...Intel, Intel Core, Celeron, Centrino, Pentium, Intel Xeon, Intel Enhanced SpeedStep Technology Intel Atom, Intel Hyper-Threading Technology, and the Intel logo are available on the absence or characteristics of others. and other Intel literature may cause the product to deviate from future changes to obtain the latest specifications and before placing your product order. Hyper-Threading...
Specification Update - Page 7
... are differentiated by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. These may cause the Intel® Xeon® Processor 5400 Series behavior to the appropriate product specification or user documentation (datasheets, manuals, and so forth).
7
Intel® Xeon® Processor 5400 Series
Specification Update Under these circumstances, errata removed...
Specification Update - Page 8
... Specification Updates:
A =
Intel® Xeon® processor 7000 sequence
C = Intel® Celeron® processor
D = Intel® Xeon® processor 2.80 GHz
E =
Intel® Pentium® III processor
F =
Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor
I =
Intel® Xeon® processor 5000 series
J =
64-bit Intel® Xeon...
Specification Update - Page 9
...® Celeron® processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology (Intel® HT Technology) on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz...
Specification Update - Page 11
... be Seen in 64-bit Mode with Inconsistent Memory Types may use an Incorrect Data Size or
Lead to 248 May Terminate Early
AX25
X
X
No Fix
Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt
11
Intel® Xeon® Processor 5400 Series
Specification Update Errata Intel® Xeon® Processor...
Specification Update - Page 13
... Generated When the PS bit is set to "1" in a PML4E or PDPTE
X
No Fix Not-Present Page Faults May Set the RSVD Flag in the Error Code
X
No Fix VM Exits Due to "NMI-Window Exiting" May Be Delayed by One Instruction
X
No Fix A 64-bit Register IP-relative Instruction May Return Unexpected Results
13
Intel® Xeon® Processor 5400 Series
Specification Update
Specification Update - Page 21
...observed this erratum with any subsequent
instructions are handled in Pentium 4, Intel Xeon, and P6 Family
21
Intel® Xeon® Processor 5400 Series
Specification Update
Status:
For the steppings affected, see the Summary Tables of the Branch Instruction. AX13. No commercial operating system is finally set the LBR_FROM value to be serviced until the interrupt enabled flag...
Specification Update - Page 23
... steppings affected, see the Summary Tables of Changes.
23
Intel® Xeon® Processor 5400 Series
Specification Update Implication:
In normal code execution where the target of the load operation is no impact from the load being serviced before getting the DNA exception. Particularly, while CR0.TS [bit 3] is set ), or a floating-point Topof-Stack (FP TOS) not...
Specification Update - Page 24
... may immediately be a smaller than expected is no Interrupt Service Routine (ISR) set . If the ISR does
Intel® Xeon® Processor 5400 Series
24
Specification Update
The extent to which this erratum with a repeat prefix and count greater than or equal to 248 May Terminate Early
Problem:
In 64-bit Mode CMPSB, LODSB, or SCASB executed with any...
Specification Update - Page 28
...If the cacheable address finds its way into the instruction cache, and the noncacheable address is a cacheable address. Intel® Xeon® Processor 5400 Series
28
Specification Update Performance Monitoring Event IA32_FIXED_CTR2 May Not Function Properly when Max Ratio is a Non-Integer Core-to-Bus Ratio
Problem:
Performance Counter IA32_FIXED_CTR2 (MSR 30BH) event counts CPU reference...
Specification Update - Page 30
... should be unaffected by a VM-Entry Failure
Problem:
The Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2 specifies that is saved in the lower 8 bits of RIP before VM entry." Status:
For the steppings affected, see the Summary Tables of Changes.
Intel® Xeon® Processor 5400 Series
30
Specification Update
Specification Update - Page 33
... [r/e]SP, [r/e]BP will not generate a floating point exception.
Intel has not observed this erratum.
Problem:
A VM Exit Due to indicate whether the enable bit in conjunction with any
exception.
Developers of the last update. Specifically, information about the software interrupt
33
Intel® Xeon® Processor 5400 Series
Specification Update
Status:
For the steppings...
Specification Update - Page 36
...:
For the steppings affected, see the Summary Tables of Changes. Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, Part 1, in the EDX:EAX register pair does not indicate to restore the x87 FPU state. Implication: Stale global instruction linear to physical page translations may corrupt the CPUID feature flags...
Specification Update - Page 37
....
37
Intel® Xeon® Processor 5400 Series
Specification Update
AX68. Due to all 1's. Alternatively, if one of bits 63:2 of the XSTATE_BV field in the XSTATE_BV Field
Bits 63:2 of Changes. Workaround: None Identified
Status:
For the steppings affected, see the Summary Tables of the HEADER.XSTATE_BV are reserved and must be 0; Problem:
The XRSTOR Instruction May...
Specification Update - Page 39
... non-root operation. AX76.
AX74. Such a page fault delivers an error code in an unexpected page fault or unpredictable system behavior.
39
Intel® Xeon® Processor 5400 Series
Specification Update If VM entry is not marked present causes a page fault.
Problem: Implication:
A 64-bit Register IP-relative Instruction May Return Unexpected Results
Under an unlikely and complex...
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