English Manual.
Page 9
... : AthlonTM 64X2 Dual-Core / AthlonTM X2 Dual-Core / AthlonTM 64 / SempronTM HyperTransport 2000/1600MT/s for AM2 CPU Up to 5200MT/s (HT3.0) for AM2+ CPU Chipset North Bridge: AMD 790GX South Bridge: AMD SB750 Memory 4 x 240-pin DDR2 DIMM sockets Support... memory Dual channel DDR2 1066*/800/667/533MHz architecture *DDR2 1066 is only supported by some AM2+ CPU Integrated Memory 128MB DDR3 SidePort Memory (Only available in A7DA-S) Audio Realtek 8-channel audio chip High Definition Audio 2/4/5.1/7.1-channel Support Jack-Sensing function LAN Broadcom...
... : AthlonTM 64X2 Dual-Core / AthlonTM X2 Dual-Core / AthlonTM 64 / SempronTM HyperTransport 2000/1600MT/s for AM2 CPU Up to 5200MT/s (HT3.0) for AM2+ CPU Chipset North Bridge: AMD 790GX South Bridge: AMD SB750 Memory 4 x 240-pin DDR2 DIMM sockets Support... memory Dual channel DDR2 1066*/800/667/533MHz architecture *DDR2 1066 is only supported by some AM2+ CPU Integrated Memory 128MB DDR3 SidePort Memory (Only available in A7DA-S) Audio Realtek 8-channel audio chip High Definition Audio 2/4/5.1/7.1-channel Support Jack-Sensing function LAN Broadcom...
English Manual.
Page 36
... Speed Adjust This item will appear only when "GFX Engine Clock Override" is set to [Enabled], it will not exceed the specified value listed in AM2+ CPU. ► GFX Engine Clock Override This item allows you to [Limit] or [Manual]. Copyright (C) 1985-2006, American Megatrends, Inc. Select [Limit], the DRAM speed...
... Speed Adjust This item will appear only when "GFX Engine Clock Override" is set to [Enabled], it will not exceed the specified value listed in AM2+ CPU. ► GFX Engine Clock Override This item allows you to [Limit] or [Manual]. Copyright (C) 1985-2006, American Megatrends, Inc. Select [Limit], the DRAM speed...
English Manual.
Page 43
For each channel : [Channel] CKE control. DRAM Timing Configuration CMOS Setup Utility - Settings are : [Auto]; [DCT 0]. (appear in AM2 CPU) Settings are two CKE pins per DRAM channel. The value that there are no transactions are pending for the chip select(s). A DIMM or a group ... transactions scheduled to any DIMM connected to the clock enable signal. A chip select or pair of the DRAMs associated with the channel are placed in AM2+ CPU) ► CAS Latency - A DIMM or a group of memory clocks it takes a DRAM to return data after the read CAS_L is enabled, if all chip...
For each channel : [Channel] CKE control. DRAM Timing Configuration CMOS Setup Utility - Settings are : [Auto]; [DCT 0]. (appear in AM2 CPU) Settings are two CKE pins per DRAM channel. The value that there are no transactions are pending for the chip select(s). A DIMM or a group ... transactions scheduled to any DIMM connected to the clock enable signal. A chip select or pair of the DRAMs associated with the channel are placed in AM2+ CPU) ► CAS Latency - A DIMM or a group of memory clocks it takes a DRAM to return data after the read CAS_L is enabled, if all chip...